Many memory systems comprise a memory controller that controls multiple memory devices. The memory controller communicates with the memory devices over an interface that carries information and control signals. Standards related to interfacing memory controllers to memory devices include, for example, Toggle 1.0 and Toggle 2.0, open NAND flash interface—ONFI 3.0, and double data rate (DDR) synchronous dynamic random-access memory (SDRAM)—DDR2 SDRAM and DDR3 SDRAM.
To ensure reliable communication, the signals that propagate along the interface (also referred to as a bus) should be properly time-aligned when arriving at either the memory controller or at the memory devices. U.S. Pat. No. 8,214,616, whose disclosure is incorporated herein by reference, describes a memory controller that may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
U.S. Patent Application Publication 2011/0216611, whose disclosure is incorporated herein by reference, describes a system that calibrates timing relationships between signals involved in performing write operations. The memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal.